View QL3060-0PB456C_3082683.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2002 quicklogic corporation www.quicklogic.com 1 ? ? device highlights high performance & high density 60,000 usable pld gates with 316 i/os 300 mhz 16-bit counters, 400 mhz datapaths 0.35 m four-layer metal non-volatile cmos process for smallest die sizes easy to use / f ast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities interfaces with both 3.3 v and 5.0 v devices pci compliant with 3.3 v and 5.0 v buses for -1/-2/-3/-4 speed grades full jtag boundary scan i/o cells with indivi dually controlled registered input path and output enables total of 316 i/o pins 308 bidirectional input/output pins, pci-compliant for 5.0 v and 3.3 v buses for -1/-2/-3/-4 speed grades eight high-drive input/distributed network pins eight low-skew distributed networks two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs ? each driven by an input-only pin six global clock/control networks available to the logic cell f1, clock set, and reset inputs and the input and i/o register clock, reset, and enable inputs as well as the output enable control ? each driven by an input- only or i/o pin, or any logic cell output or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz figure 1: 1,584 pasic 3 logic cells ql3060 pasic 3 fpga data sheet 60,000 usable pld ga te pasic 3 fpga combining high performance and high density
2 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d architecture overview the ql3060 is a 60,000 usable pld gate member of the pasic 3 family of fpgas. pasic 3 fpgas are fabricated on a 0.35 m four-layer metal process using quicklogic ? 's patented vialink ? technology to provide a un ique combination of high performance, high density, low cost, and extr eme ease-of-use. the ql3060 contains 1,584 logic cells. with a maximum of 316 i/os, the ql3060 is available in 208-pqfp and 456-pin pbga packages. software support for the complete pasic 3 family, including the ql3060, is available through three basic pack ages. the turnkey quick works ? package provides the most complete fpga software so lution from design entry to logi c synthesis, to place and route, to simulation. the quicktools tm for workstations package provides a solution for designers who use cadence ? , exemplar tm , mentor ? , synopsys ? , synplicity ? , viewlogic tm , aldec tm , or other third-party tools for design entry, synthesis, or simulation.
? 2002 quicklogic corporation www.quicklogic.com 3 ql3060 pasic 3 fpga data sheet rev d electrical specifications ac characteristics at v cc = 3.3 v, ta = 25 c (k = 1.00) to calculate delays, multiply the appropriate k factor from table 7 by the numbers provided in table 1 through table 5 . table 1: logic cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriat e delay factor, k, for speed gr ade, voltage, and temperature settings as specified in table 7 . 1 2 3 4 8 t pd combinatorial delay b b. these limits are derived from a representative selection of the slowest paths through the pasic 3 logic cell including typical net delays. worst case delay values for specific paths should be de- termined from timing analysis of your particular design. 1.4 1.7 1.9 2.2 3.2 t su setup time b 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t set set delay 1.0 1.3 1.5 1.8 2.8 t reset reset delay 0.8 1.1 1.3 1.6 2.6 t sw set width 1.9 1.9 1.9 1.9 1.9 t rw reset width 1.8 1.8 1.8 1.8 1.8 table 2: input-only/clock cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagatio n delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor , k, for speed grade, voltage, and tempera- ture settings as specified in table 7 . 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t lclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t lrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
4 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d table 3: clock cells symbol parameter propagation delays (ns) loads per half column a a. the array distributed networks consist of 40 half columns and the global distributed networks con- sist of 44 half columns, each driven by an in dependent buffer. the number of half columns used does not affect clock buffer delay. the array cl ock has up to eight loads per half column. the glo- bal clock has up to 11 loads per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 table 4: input-only i/o cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propaga tion delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage, and temperature settings as specified in table 7 . 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 t loclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t lorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0
? 2002 quicklogic corporation www.quicklogic.com 5 ql3060 pasic 3 fpga data sheet rev d figure 2: loads used for t pxz table 5: output-only i/o cells symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a a. the loads presented in figure 2 are used for t pxz : 2.0 - - - - t plz output delay low to tri-state 1.2 - - - - 1? 1? t phz t plz 5 pf 5 pf
6 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d dc characteristics the dc specifications are provided in table 6 through table 8 . table 6: absolute maximum ratings parameter value parameter value v cc voltag e -0.5 v to 4.6 v dc input current 20 ma v ccio voltag e -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v storage temperature -65c to +150c latch-up immunity 200 ma lead temperature 300c table 7: operating range symbol parameter military industrial commercial unit min max min max min max v cc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -0 speed grade - - 0.43 1.90 0.46 1.85 n/a -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 speed grade 0.43 0.90 0.46 0.88 n/a -4 speed grade 0.43 0.82 0.46 0.80 n/a
? 2002 quicklogic corporation www.quicklogic.com 7 ql3060 pasic 3 fpga data sheet rev d table 8: dc characteristics symbol parameter conditions min max units v ih input high voltage 0.5 v cc v ccio +0.5 v v il input low voltage -0.5 0.3 v cc v v oh output high voltage i oh = -12 ma 2.4 v i oh = -500 a 0.9 v cc v v ol output low voltage i ol = 16 ma a a. applies only to -1/-2/-3/-4 commercial grade de vices. these speed grades are also pci-compliant. all other devices have 8 ma i ol specifications. 0.45 v i ol = 1.5 ma 0.1 v cc v i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd -10 10 a c i input capacitance b b. capacitance is sample tested only. clock pins are 12 pf maximum. 10 pf i os output short circuit current c c. only one output at a time. duration should not exceed 30 seconds. v o = gnd -15 -180 ma v o = v cc 40 210 ma i cc d.c. supply current d d. for -1/-2/-3/-4 commercial grade devices only. maximum i cc is 3 ma for -0 commercial grade and all industrial grade devices. and 5 ma for all military grade devices. for ac conditions, contact quicklog- ic customer applications group (see contact information ). v i , v io = v ccio or gnd 0.50 (typ) 2 ma i ccio d.c. supply current on v ccio 0 100 a
8 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d kv and kt graphs figure 3: voltage factor vs. supply voltage figure 4: temperature factor vs. operating temperature 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 voltage factor vs. supply voltage supply voltage (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temperature factor vs. operating temperature junction temperature c kt
? 2002 quicklogic corporation www.quicklogic.com 9 ql3060 pasic 3 fpga data sheet rev d power-up sequencing figure 5: power-up requirements the following requirements mu st be met when powering up the device (refer to figure 5 ): when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. deviation from this recommendation can cause pe rmanent damage to the device. v ccio must lead v cc when ramping the device. the power supply must take greater th an or equal to 400 s to reach v cc . ramping to v cc /v ccio earlier than 400 s can cause th e device to behave improperly. an internal diode is present in-between v cc and v ccio , as shown in figure 6 . figure 6: internal diode between v cc and v ccio voltage v ccio v cc (v ccio -v cc ) max time 400 us v cc v cc v ccio internal logic cells, ram blocks, etc io cells
10 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d jtag figure 7: jtag block diagram microprocessors and application specific inte grated circuits (asics) pose many design challenges, not the least of whic h concerns the accessibility of test points. the joint test access group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allo ws complete observatio n and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instru ction register (ir); these allow users to run three required tests, along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
? 2002 quicklogic corporation www.quicklogic.com 11 ql3060 pasic 3 fpga data sheet rev d the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap's te st data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded wi th test patterns (via the sample/preload instruction), and input boundary cells capture the input da ta for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while select ing the boundary scan regist er to be connected between the tdi and tdo pins. for this test, the boun dary scan register can be accessed via a data scan operation, allowing users to sample the function al data entering and leaving the device. bypass instruction. the bypass instruction allows da ta to skip a device's boundary scan entirely, so the data passes through the bypass regi ster. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affectin g the operation of the device.
12 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d pin descriptions ordering information * contact quicklogic regarding availability (see contact information ) table 9: pin descriptions pin function description tdi test data in for jtag hold high during normal operation. connect to v cc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. v cc power supply pin connect to 3.3 v supply. v ccio input voltage tolerance pin connect to 5.0 v supply if 5 v input tolerance is required, otherwise connect to 3.3 v supply. gnd ground pin connect to ground. ql 3060 - 1 pq208 c quicklogic device pasic 3 device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow operating range c = commercial i = industrial m = military package code pq208 = 208-pin pqfp pb456 = 456-pin pbga
? 2002 quicklogic corporation www.quicklogic.com 13 ql3060 pasic 3 fpga data sheet rev d 208 pqfp pinout diagram figure 8: top view of 208 pin pqfp pin 1 pin 53 pin 105 pin 157 ql3060-1pq208c pasic 3
14 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d 208 pqfp pinout table table 10: 208 pqfp pinout table 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 i/o 43 gnd 84 i/o 125 i/o 168 i/o 1 i/o 44 i/o 85 i/o 126 i/o 169 i/o 2 i/o 45 i/o 86 i/o 127 gnd nc i/o 3 i/o 46 i/o 87 i/o 128 i/o 170 i/o 4 i/o 47 i/o 88 i/o nc i/o 171 i/o 5 i/o 48 i/o 89 i/o 129 gclk / i 172 i/o nc i/o nc i/o 90 i/o 130 aclk / i 173 i/o 6 i/o 49 i/o 91 i/o 131 v cc 174 i/o 7 i/o 50 i/o 92 i/o 132 gclk / i 175 i/o 8 i/o 51 i/o nc i/o 133 gclk / i nc i/o 9 i/o 52 i/o 93 i/o 134 v cc 176 i/o 10 v cc 53 i/o 94 i/o 135 i/o 177 gnd 11 i/o 54 tdi 95 gnd 136 i/o 178 i/o 12 gnd nc i/o 96 i/o nc i/o 179 i/o 13 i/o nc i/o 97 v cc 137 i/o nc i/o 14 i/o 55 i/o 98 i/o nc gnd 180 i/o nc i/o 56 i/o 99 i/o 138 i/o 181 i/o 15 i/o nc i/o 100 i/o 139 i/o 182 gnd 16 i/o 57 i/o nc i/o 140 i/o nc v cc 17 i/o 58 i/o 101 i/o 141 i/o 183 i/o 18 i/o 59 gnd nc i/o 142 i/o 184 i/o 19 i/o 60 i/o 102 i/o nc i/o 185 i/o 20 i/o 61 v cc nc i/o 143 i/o 186 i/o nc i/o 62 i/o nc i/o 144 i/o 187 v ccio 21 i/o 63 i/o 103 trstb 145 v cc 188 i/o 22 i/o 64 i/o 104 tms nc i/o nc i/o 23 gnd nc i/o 105 i/o 146 i/o 189 i/o 24 i/o 65 i/o nc i/o 147 gnd 190 i/o 25 gclk / i 66 i/o 106 i/o 148 i/o 191 i/o 26 aclk / i 67 i/o 107 i/o 149 i/o 192 i/o 27 v cc nc i/o 108 i/o 150 i/o 193 i/o 28 gclk / i 68 i/o 109 i/o 151 i/o 194 i/o 29 gclk / i 69 i/o nc i/o 152 i/o nc i/o 30 v cc 70 i/o 110 i/o 153 i/o 195 i/o 31 i/o nc i/o 111 i/o 154 i/o 196 i/o 32 i/o 71 i/o 112 i/o 155 i/o 197 i/o nc gnd nc i/o 113 i/o 156 i/o 198 i/o 33 i/o 72 i/o 114 v cc 157 tck nc i/o nc i/o 73 gnd 115 i/o 158 stm 199 gnd 34 i/o 74 i/o 116 gnd nc i/o 200 i/o 35 i/o nc v cc 117 i/o 159 i/o 201 v cc 36 i/o 75 i/o nc i/o 160 i/o 202 i/o nc i/o 76 i/o 118 i/o 161 i/o 203 i/o 37 i/o 77 i/o 119 i/o 162 i/o 204 i/o 38 i/o 78 gnd 120 i/o 163 gnd 205 i/o 39 i/o 79 i/o 121 i/o 164 i/o 206 i/o nc i/o 80 i/o nc i/o 165 v cc 207 tdo 40 i/o 81 i/o 122 i/o 166 i/o 41 v cc 82 i/o 123 i/o nc i/o 42 i/o 83 v ccio 124 i/o 167 i/o
? 2002 quicklogic corporation www.quicklogic.com 15 ql3060 pasic 3 fpga data sheet rev d 456 pbga pinout diagram figure 9: 456-pin pbga pinout diagram ql3060-1pb456c pasic 3 bottom view pin a1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
16 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d 456 pbga pinout table table 11: 456 pbga pinout table 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 i/o m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 i/o m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 v cc j1 i/o m26 i/o a9 i/o c8 i/o e7 gnd j2 i/o n1 gclk/i a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 v ccio c11 i/o e10 i/o j5 gnd n4 gclk/i a13 i/o c12 i/o e11 gnd j22 nc n5 v cc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 i/o c14 i/o e13 v cc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 i/o c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 i/o e16 gnd k1 i/o n15 gnd/therm a19 i/o c18 i/o e17 nc k2 i/o n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 i/o c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 v cc n24 i/o a23 i/o c22 i/o e21 v cc k22 gnd n25 i/o a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 i/o p2 i/o b1 i/o c26 i/o e25 i/o k26 i/o p3 i/o b2 i/o d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 i/o d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 i/o d4 gnd f3 i/o l4 i/o p12 gnd/therm b6 i/o d5 i/o f4 nc l5 nc p13 gnd/therm b7 i/o d6 nc f5 v cc l11 gnd/therm p14 gnd/therm b8 i/o d7 i/o f22 v cc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 i/o d9 gnd f24 i/o l14 gnd/therm p22 nc b11 i/o d10 i/o f25 i/o l15 gnd/therm p23 gclk / i b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 gclk / i b13 i/o d12 gnd g1 i/o l22 nc p25 i/o b14 i/o d13 i/o g2 i/o l23 i/o p26 aclk / i b15 i/o d14 i/o g3 i/o l24 i/o r1 i/o b16 i/o d15 gnd g4 i/o l25 i/o r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 aclk / i r4 nc b19 i/o d18 gnd g23 i/o m2 gclk/i r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 i/o g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 i/o d22 i/o h1 i/o m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 i/o m13 gnd/therm r16 gnd/therm (sheet 1 of 2)
? 2002 quicklogic corporation www.quicklogic.com 17 ql3060 pasic 3 fpga data sheet rev d r22 v cc w1 i/o ab12 nc ad1 i/o ae16 i/o r23 nc w2 i/o ab13 i/o ad2 nc ae17 i/o r24 i/o w3 i/o ab14 gnd ad3 i/o ae18 i/o r25 i/o w4 i/o ab15 v cc ad4 i/o ae19 i/o r26 gclk / i w5 nc ab16 i/o ad5 i/o ae20 i/o t1 i/o w22 nc ab17 nc ad6 i/o ae21 i/o t2 i/o w23 i/o ab18 v cc ad7 i/o ae22 i/o t3 i/o w24 i/o ab19 gnd ad8 i/o ae23 nc t4 i/o w25 i/o ab20 nc ad9 i/o ae24 tms t5 v cc w26 i/o ab21 v cc ad10 i/o ae25 i/o t11 gnd/thermal y1 i/o ab22 gnd ad11 i/o ae26 i/o t12 gnd/thermal y2 i/o ab23 i/o ad12 i/o af1 i/o t13 gnd/thermal y3 i/o ab24 i/o ad13 i/o af2 i/o t14 gnd/thermal y4 i/o ab25 i/o ad14 i/o af3 i/o t15 gnd/thermal y5 i/o ab26 i/o ad15 i/o af4 i/o t16 gnd/thermal y22 gnd ac1 i/o ad16 i/o af5 i/o t22 gnd y23 i/o ac2 i/o ad17 i/o af6 i/o t23 i/o y24 i/o ac3 nc ad18 i/o af7 i/o t24 i/o y25 i/o ac4 gnd ad19 i/o af8 i/o t25 i/o y26 i/o ac5 i/o ad20 i/o af9 i/o t26 i/o aa1 i/o ac6 nc ad21 i/o af10 i/o u1 i/o aa2 i/o ac7 i/o ad22 i/o af11 i/o u2 i/o aa3 nc ac8 i/o ad23 trstb af12 i/o u3 i/o aa4 nc ac9 nc ad24 i/o af13 i/o u4 i/o aa5 v cc ac10 i/o ad25 i/o af14 i/o u5 gnd aa22 v cc ac11 i/o ad26 i/o af15 i/o u22 nc aa23 nc ac12 nc ae1 tdi af16 i/o u23 i/o aa24 i/o ac13 i/o ae2 i/o af17 i/o u24 i/o aa25 i/o ac14 v ccio ae3 i/o af18 i/o u25 i/o aa26 i/o ac15 nc ae4 i/o af19 i/o u26 i/o ab1 i/o ac16 i/o ae5 i/o af20 i/o v1 i/o ab2 i/o ac17 i/o ae6 i/o af21 i/o v2 i/o ab3 i/o ac18 nc ae7 i/o af22 i/o v3 i/o ab4 i/o ac19 i/o ae8 i/o af23 i/o v4 nc ab5 gnd ac20 i/o ae9 i/o af24 i/o v5 nc ab6 v cc ac21 i/o ae10 i/o af25 i/o v22 gnd ab7 nc ac22 nc ae11 i/o af26 i/o v23 nc ab8 nc ac23 gnd ae12 i/o v24 i/o ab9 nc ac24 i/o ae13 i/o v25 i/o ab10 v cc ac25 i/o ae14 i/o v26 i/o ab11 gnd ac26 i/o ae15 i/o table 11: 456 pbga pinout table (continued) 456 function 456 function 456 function 456 function 456 function (sheet 2 of 2)
18 www.quicklogic.com ? 2002 quicklogic corporation ql3060 pasic 3 fpga data sheet rev d 456 pbga mechanical drawing figure 10: 456 pbga mechanical drawing
? 2002 quicklogic corporation www.quicklogic.com 19 ql3060 pasic 3 fpga data sheet rev d contact information telephone: 408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.qui cklogic.com/ revision history copyright information copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this product brief, and the a ccompanying software programs are protected by copyright. all rights are rese rved by quicklogic corporation. quicklogic corporation reserves the right to make peri odic modifications of this product without obligation to notify any person or entity of such revision. co pying, duplicating, selling, or otherwise distributing any part of this pro duct without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic, quick works, pasic, and vialink are registered trademarks of quicklogic corporation. verilog is a registered trademark of cadence design systems, inc. all trademarks and registered trademarks are the property of their respective owners. table 12: revision history revision date comments a not avail. first release. b not avail. c may 2001 update of ac/dc specs and reformat d june 2002 added kfactor, power-up, jtag and mechanical drawing information. reformatted.

▲Up To Search▲

Price & Availability of QL3060-0PB456C

	To Download QL3060-0PB456C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .